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acpl-h342 and acpl-k342 2.5 amp output current igbt gate drive optocoupler with active miller clamp, rail-to-rail output voltage and uvlo in stretched so8 data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the acpl-h342/acpl-k342 contains an algaas led, which is optically coupled to an integrated circuit with a power output stage. this optocoupler is ideally suited for driving power igbts and mosfets used in motor control inverter applications. the high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. the voltage and high peak output current supplied by this optocoupler make it ideally suited for direct driving igbt with ratings up to 1200v/150a. for igbts with higher ratings, the acpl-h342/acpl-k342 can be used to drive a discrete power stage which drives the igbt gate. the acpl-h342 and acpl-k342 have the highest insulation voltage of v iorm = 891vpeak and 1140vpeak respectively in the iec/ en/din en 60747-5-5. functional diagram features ? 2.5 a maximum peak output current ? 2.0a minimum peak output current ? built-in active miller clamp ? rail-to-rail output voltage ? fast propagation delay to minimize dead time ? t phl < t plh to provide anti-cross conduction ? led input threshold current hysteresis ? i cc = 2.5 ma maximum supply current to allow boot- strap power supply ? under voltage lock-out protection (uvlo) with hysteresis ? 40 kv/ s minimum common mode rejection (cmr) at v cm = 1500 v ? wide operating v cc range: 15 to 30 volts ? industrial temperature range: -40c to 105c ? safety approval: C ul recognized 3750/5000 v rms for 1min. C csa C iec/en/din en 60747-5-5 v iorm = 891/1140 vpeak applications ? igbt/mosfet gate drive ? ac and brushless dc motor drives ? renewable energy inverters ? industrial inverters ? switching power supplies v cc v out v clamp v ee 1 2 3 4 8 7 6 5 cathode nc anode nc v c l a m p v c l a m p note: design note: a 1 f bypass capacitor must be connected between pins v cc and v ee . truth table led v cc C v ee positive going (i.e., turn-on) v cc C v ee negative going (i.e., turn-off) v o v clamp off 0 C 30v 0 C 30v low low on 0 C 11v 0 C 9.5v low low on 11 C 13.5v 9.5 C 12v transition transition on 13.5 C 30v 12 C 30v high hi-z lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product
2 ordering information acpl-h342 is ul recognized with 3750 v rms for 1 minute per ul1577. acpl-k342 is ul recognized with 5000 v rms for 1 minute per ul1577. part number option (rohs compliant) package surface mount tape & reel ul 5000 v rms /1 minute rating iec/en/din en 60747-5-5 quantity acpl-h342 -000e stretched so-8 x 80 per tube -500e x x 1000 per reel -060e x x 80 per tube -560e x x x 1000 per reel acpl-k342 -000e stretched so-8 x x 80 per tube -500e x x x 1000 per reel -060e x x x 80 per tube -560e x x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: acpl-h342-560e to order product of stretched so-8 surface mount package in tape and reel packaging with iec/en/ din en 60747-5-5 safety approval and rohs compliant. example 2: acpl-k342-000e to order product of stretched so-8 surface mount package in tube packaging with ul 5000 v rms /1 minute and rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 lead coplanarity = 0.1mm [0.004 inches] floating lead protusions max. 0.25 [0.0] dimensions in millimeters [inches] 0.381 + 0.127 0 0.015 + 0.005 5.850 + 0. 254 0 0.230 + 0.010 0.450 0.018 7.620 0.300 6.807 0.268 1.270 0.050 7 7 7 7 45 5 nom. 1.590 0.127 0.063 0.005 0.200 0.100 0.008 0.004 1 0.250 0.040 0.010 9.7 0.25 0.382 0.010 0.254 0.050 0.010 0.002 3.180 0.127 0.125 0.005 10.7 (0.421) 1.27 (0.05) 0.76 (0.03) 2.16 (0.085) land pattern recommendation 2 3 4 5 6 7 8 lead coplanarity = 0.1mm [0.004 inches] floating lead protusions max. 0.25 [0.0] dimensions in millimeters [inches] 5.850 + 0.25 0 0.230 + 0.010 0.000 ? ? ? ? 0.450 0.018 ? ? ? ? 7.62 0.300 ? ? ? ? 35 nom. 0.381 0.13 0.015 0.005 ? ? ? ? 1 6.807 0.127 0.268 0.005 ? ? ? ? 1.590 0.127 0.063 0.005 ? ? ? ? 3.180 0.127 0.125 0.005 ? ? ? ? 0.254 0.050 0.010 0.002 ? ? ? ? 11.5 0.250 0.453 0.010 ? ? ? ? 7 7 45 0.200 0.100 0.008 0.004 ? ? ? ? 0.750 0.25 0.0295 0.01 ? ? ? ? 7 7 1.270bsg 0.050 ? ? ? ? 12.65 (0.5) 1.27 (0.05) 0.76 (0.03) 1.905 (0.075) land pattern recommendation package outline drawings acpl-h342 outline drawing acpl-k342 outline drawing
4 table 1. iec/en/din en 60747-5-5 insulation characteristics* (acpl-h342 / acpl-k342 option 060) description symbol acpl-h342 option 060 acpl-k342 option 060 unit installation classifcation per din vde 0110/39, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 450 v rms i C iv i C iv i C iii i C iv i C iv i C iv for rated mains voltage 600 v rms i C iii i C iv for rated mains voltage 1000 v rms i C iii climatic classifcation 40/105/21 40/105/21 pollution degree (din vde 0110/39) 2 2 maximum working insulation voltage v iorm 891 1140 v peak input to output test voltage, method b* v iorm x 1.875=v pr , 100% production test with t m =1 sec, partial discharge < 5 pc v pr 1671 2137 v peak input to output test voltage, method a* v iorm x 1.6=v pr , type and sample test, t m =10 sec, partial discharge < 5 pc v pr 1426 1824 v peak highest allowable overvoltage* (transient overvoltage t ini = 60 sec) v iotm 6000 8000 v peak safety-limiting values C maximum values allowed in the event of a failure case temperature input current output power t s i s, input p s, output 175 230 600 175 230 600 c ma mw insulation resistance at t s , v io = 500 v r s >10 9 >10 9 w * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section, (iec/en/ din en 60747-5-5) for a detailed description of method a and method b partial discharge test profles. note: these optocouplers are suitable for safe electrical isolation only within the safety limit data. maintenance of the safety data shall be ensured by means of protective circuits. surface mount classifcation is class a in accordance with cecc 00802. recommended pb-free ir profle recommended refow condition as per jedec standard, j-std-020 (latest revision). non- halide flux should be used. regulatory information the acpl-h342 / acpl-k342 is approved by the following organizations: ul recognized under ul 1577, component recognition program up to v iso = 3750 v rms (acpl-h342) and v iso = 5000 v rms (acpl-k342), file 55361 csa csa component acceptance notice #5, file ca 88324 iec/en/din en 60747-5-5 (acpl-h342/k342 option 060 only) maximum working insulation voltage viorm = 891v peak (acpl-h342) and viorm = 1140 v peak (acpl-k342)
5 table 2. insulation and safety related specifcations parameter symbol acpl-h342 acpl-k342 units conditions minimum external air gap (clearance) l(101) 7.0 8.0 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 8.0 8.0 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 0.08 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti > 175 > 175 v din iec 112/vde 0303 part 1 isolation group iiia iiia material group (din vde 0110, 1/89, table 1) notes: 1. all avago data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specifed for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fllets of the input and output leads must be considered (the recommended land pattern does not necessarily meet the minimum creepage of the device). there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. table 3. absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 105 c output ic junction temperature t j 125 c average input current i f(avg) 25 ma 1 peak transient input current (<1 s pulse width, 300pps) i f(tran) 1 a reverse input voltage v r 5 v high peak output current i oh(peak) 2.5 a 2 low peak output current i ol(peak) 2.5 a 2 peak clamp sink current i clamp 2.5 a 2 total output supply voltage (v cc - v ee ) 0 35 v output voltage v o(peak) -0.5 v cc v output ic power dissipation p o 500 mw 3 total power dissipation p t 550 mw 4 lead solder temperature 260c for 10 sec., 1.6 mm below seating plane table 4. recommended operating conditions parameter symbol min. max. units note operating temperature t a - 40 105 c output supply voltage (v cc - v ee ) 15 30 v input current (on) i f(on) 7 16 ma input voltage (off) v f(off) - 3.6 0.8 v
6 table 5. electrical specifcations (dc) unless otherwise noted, all typical values are at t a = 25c, v cc - v ee = 30 v, v ee = ground; all minimum/maximum speci - fcations are at recommended operating conditions (t a = -40 to 105c, i f(on) = 7 to 16 ma, v f(off) = -3.6 to 0.8 v, v cc = 15 to 30 v, v ee = ground). parameter symbol min. typ. max. units test conditions fig. note high level peak output current i oh -0.5 -1.2 a v o = v cc C 4 3, 4, 23 5 -2.0 a v o = v cc C 15 2 low level peak output current i ol 0.5 2.7 a v o = v ee + 2.5v 6, 7, 24 5 2.0 a v o = v ee + 15v 2 high output transistor rds(on) r ds,oh 2.6 5.0 w i oh = -2.0a 8 low output transistor rds(on) r ds,ol 0.8 2.0 w i ol = 2.0a 9 clamp output peak current i clamp 1.0 2.5 a v o = v ee + 2.5 14, 16, 27 2 clamp pin threshold v tclamp 2.3 v 15,16, 28 clamp output transistor rds(on) r ds,clamp 0.8 2.0 w i clamp = 1.5 a high level output voltage v oh v cc -2.0 v cc -0.80 v i o = -100 ma 2, 4, 25 6, 7 high level output voltage v oh v cc v i o = 0 ma , i f =10 ma 1 low level output voltage v ol 0.07 0.25 v i o = 100 ma 5, 7, 26 high level supply current i cch 1.68 2.5 ma r g = 10 w , c g = 25 nf, i f = 10 ma, 10, 11 low level supply current i ccl 2.0 2.5 ma r g = 10 w , c g = 25 nf, i f = 0 ma threshold input current low to high i flh 0.5 1.5 4.0 ma r g = 10 w , c g = 25 nf, v o > 5 v 12, 13, 29 threshold input voltage high to low v fhl 0.8 v input forward voltage v f 1.2 1.55 1.95 v i f = 10 ma 22 temperature coefcient of input forward voltage v f / t a -1.7 mv/c input reverse breakdown voltage bv r 5 v i r = 100 a input capacitance c in 70 pf f = 1 mhz, v f = 0 v uvlo threshold v uvlo+ 11.0 12.3 13.5 v v o > 5 v, i f = 10 ma 30 v uvlo- 9.5 10.7 12.0 uvlo hysteresis uvlo hys 1.4
7 table 6. switching specifcations (ac) unless otherwise noted, all typical values are at t a = 25c, v cc - v ee = 30 v, v ee = ground; all minimum/maximum speci - fcations are at recommended operating conditions (t a = -40 to 105c, i f(on) = 7 to 16 ma, v f(off) = -3.6 to 0.8 v, v cc = 15 to 30 v, v ee = ground). parameter symbol min. typ. max. units test conditions fig. note propagation delay time to high output level t plh 0.100 0.260 0.350 s r g = 10 w , c g = 25 nf, f = 20 khz , duty cycle = 50%, i f = 7 ma to 16 ma, v cc = 15 v to 30v 17, 18, 19, 20, 21, 31 15 propagation delay time to low output level t phl 0.050 0.145 0.250 s propagation delay diference between any two parts pdd (t phl - t plh ) -0.010 -0.100 -0.200 s 39, 40 11 rise time t r 22 ns v cc = 30 v 31 fall time t f 18 ns output high level common mode transient immunity |cm h | 40 50 kv/ s t a = 25 c, i f = 10 ma, v cc = 30 v, v cm = 1500 v with split resistors 32 12, 13 25 35 t a = 25 c, i f = 10 ma, v cc = 30 v, v cm = 1000 v without split resistors output low level common mode transient immunity |cm l | 40 50 kv/ s t a = 25 c, v f = 0 v, v cc = 30 v, v cm = 1500 v with split resistors, 32 12, 14 25 35 t a = 25 c, v f = 0 v, v cc = 30 v, v cm = 1000 v without split resistors table 7. package characteristics unless otherwise noted, all typical values are at t a = 25 c; all minimum/maximum specifcations are at recommended operating conditions. parameter symbol device min. typ. max. units test conditions fig. note input-output momentary withstand voltage* v iso acpl-h342 3750 v rms rh < 50%, t = 1 min., t a = 25 c 8,10 acpl-k342 5000 v rms rh < 50%, t = 1 min., t a = 25 c 9,10 input-output resistance r i-o >50 12 w v i-o = 500 v dc 10 input-output capacitance c i-o 0.2 pf f =1 mhz led-to-ambient thermal resistance r 11 145 c/w thermal model in application notes below 16 led-to-detector thermal resistance r 12 , r 21 25, 38 detector-to-ambient thermal resistance r 22 46 * the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating, refer to your equipment level safety specifcation or avago technologies application note 1074 entitled optocoupler input-output endurance voltage. notes: 1. derate linearly above 70 c free-air temperature at a rate of 0.3 ma/ c. 2. maximum pulse width = 10 s 3. derate linearly above 85c free-air temperature at a rate of 12.5 mw/c. 4. derate linearly above 85c free-air temperature at a rate of 13.75 mw/c. the maximum led junction temperature should not exceed 125c. 5. maximum pulse width = 50 s. 6. in this test v oh is measured with a dc load current. when driving capacitive loads v oh will approach v cc as i oh approaches zero amps. 7. maximum pulse width = 1 ms. 8. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 4500 vrms for 1 second (leakage detection current limit, i i-o 5 a). 9. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 6000 vrms for 1 second (leakage detection current limit, i i-o 5 a). 10. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 11. the diference between t phl and t plh between any two acpl-h342 parts under the same test condition. 12. pins 2 and 4 need to be connected to led common. 13. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in the high state (i.e., v o > 15.0 v). 14. common mode transient immunity in a low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < 1.0 v). 15. this load condition approximates the gate load of a 1200v/150a igbt. 16. the device was mounted on a high conductivity test board as per jedec 51-7.
8 figure 2. v oh vs. temperature. figure 1. high ouput rail voltage vs. temperature. figure 4. i oh vs. v oh . figure 3. i oh vs. temperature. figure 6. i ol vs. temperature. figure 5. v ol vs. temperature. 29.966 29.967 29.968 29.969 29.97 29.971 29.972 29.973 29.974 29.975 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 t a - temperature - c t a - temperature - c -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 t a - temperature - c -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 t a - temperature - c t a - temperature - c v oh - high output rail voltage- v -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 i oh - output high current - a v ol - output low voltage - v i ol - output low current - a -2.50 -2.00 -1.50 -1.00 -0.50 0.00 0.00 1.00 2.00 3.00 4.00 5.00 6.00 (v oh - v cc ) - high output voltage drop - v i oh - output high current - a 0 0.02 0.04 0.06 0.08 0.1 0.12 0 0.5 1 1.5 2 2.5 3 3.5 4 i f = 10 ma v cc = 30 v v ee = 0 v (v oh - v cc ) - high output voltage drop - v i f = 10 ma i out = -100 ma v cc = 15 to 30 v v ee = 0 v i f = 10 ma v out = (v cc 4 v) v cc = 15 to 30 v v ee = 0 v t a = 25c v f(off) = 0 v v out = 2.5 v v cc = 15 to 30 v v ee = 0 v v f(off) = 0 v i out = 100 ma v cc = 15 to 30 v v ee = 0 v -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
9 figure 8. r ds,oh vs. temperature. figure 7. i ol vs. v ol figure 10. i cc vs. temperarure. figure 9. r ds,ol vs. temperature. figure 12. i flh hysteresis. figure 11. i cc vs. v cc . 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 1 2 3 v ol - output low voltage - v i ol - output low current - a 0 0.5 1 1.5 2 2.5 3 3.5 r ds,oh - high output transistor r ds (on) - ? 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 r ds,ol - low output transistor r ds (on) - ? 0 0.5 1 1.5 2 2.5 i cc - supply current -ma 0 0.5 1 1.5 2 2.5 15 20 25 30 v cc - supply voltage - v i cc - supply current - ma 0 5 10 15 20 25 30 35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i flh - low to high current threshold - ma v o - output voltage- v v f(off) = 0 v i out = 2 a v cc = 15 to 30 v v ee = 0 v t a = 25c v cc = 30 v v ee = 0 v i f = 10 ma i out = -2 a v cc = 15 to 30 v v ee = 0 v i cch i ccl i flh on i flh off i cch i ccl t a = 25c v f(off) = 0 v i f = 10 ma for i cch i f = 0 ma for i ccl v cc = 30 v v ee = 0 v i f = 10 ma for i cch i f = 0 ma for i ccl t a = 25c v ee = 0 v -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 t a - temperature - c -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 t a - temperature - c -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 t a - temperature - c
10 figure 14. i clamp vs. temperature. figure 13. i flh vs. temperature. figure 16. i clamp vs. v tclamp . figure 15. v tclamp vs. temperature. figure 18. propagation delay vs. i f . figure 17. propagation delay vs. v cc . 0.0 0.5 1.0 1.5 2.0 2.5 i flh - low to high current threshold - ma 0 0.5 1 1.5 2 2.5 3 3.5 i clamp - clamp output peak current - a 0 0.5 1 1.5 2 2.5 3 3.5 v tclamp - clamp pin threshold - v -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1 1.5 2 2.5 v tclamp - clamp pin threshold - v i clamp - clamp output peak current - a 0 50 100 150 200 250 300 15 20 25 30 v cc - supply voltage - v t p - propagation delay - ns 0 50 100 150 200 250 300 6 8 10 12 14 16 i f - forwar led current - ma t p - propagation delay - ns i flh on i flh off t phl t plh v cc = 30 v, v ee = 0 v t a = 25c r g = 10 ?, c g = 25 nf duty cycle = 50% f = 20 khz t phl t plh v cc = 15 to 30 v v ee = 0 v v out = 2.5 v v cc = 15 to 30 v v ee = 0 v v cc = 15 v v ee = 0 v t a = 25c i f = 7 ma t a = 25c r g = 10 ?, c g = 25 nf duty cycle = 50% f = 20 khz -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 t a - temperature - c -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 t a - temperature - c -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 t a - temperature - c
11 figure 20. propagation delay vs. rg. figure 19. propagation delay vs. temperature. figure 22. input current vs. forward voltage. figure 21. propagation delay vs. cg. 0 50 100 150 200 250 300 350 t p - propagation delay - ns 0 50 100 150 200 250 300 r g - series load resistance - ? t p - propagation delay - ns 0 50 100 150 200 250 300 0 5 10 15 20 25 30 35 40 45 50 c g - load capacitance - nf t p - propagation delay - ns 0.1 1 10 100 1.4 1.45 1.5 1.55 1.6 1.65 v f - forward voltage - volts i f - forward current - ma i f = 7 ma v cc = 30 v, v ee = 0 v r g = 10 ?, c g = 25 nf duty cycle = 50% f = 20 khz t phl t plh v cc = 30 v, v ee = 0 v i f = 7 ma, t a = 25c c g = 25 nf duty cycle = 50% f = 20 khz t plh t phl t plh t phl v cc = 30 v, v ee = 0 v i f = 7 ma, t a = 25c r g = 10 ? duty cycle = 50% f = 20 khz -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 t a - temperature - c 0 5 10 15 20 25 30 35 40 45 50
12 i f = 10ma + _ + _ 1f 4v pulsed i oh v cc = 15 to 30v 1 2 3 4 8 7 6 5 + _ + _ v c l a m p v c l a m p + _ + _ 1f 2.5v pulsed i ol v cc = 15 to 30v 1 2 3 4 8 7 6 5 + _ + _ v c l a m p v c l a m p i f = 10ma + _ 1f 100ma v cc = 15 to 30v v oh 1 2 3 4 8 7 6 5 + _ v c l a m p v c l a m p + _ 1f 100ma v cc = 15 to 30v v ol 1 2 3 4 8 7 6 5 + _ v c l a m p v c l a m p figure 23. i oh test circuit. figure 24. i ol test circuit. figure 25. v oh test circuit. figure 26. v ol test circuit.
13 + 1f 2.5v pulsed i clamp v cc = 15 to 30v 1 2 3 4 8 7 6 5 + _ _ + _ v c l a m p v c l a m p + _ 1f 3v v cc = 15 to 30v 1 2 3 4 8 7 6 5 + _ 1k? v tclamp + _ + _ v c l a m p v c l a m p i f + _ 1f v cc = 15 to 30v v o > 5v 1 2 3 4 8 7 6 5 10? 25nf + _ v c l a m p v c l a m p i f = 10ma + _ 1f v o > 5v 1 2 3 4 8 7 6 5 + _ v c l a m p v c l a m p figure 27. i clamp test circuit. figure 28. v tclamp test circuit. figure 29. i flh test circuit. figure 30. uvlo test circuit.
14 figure 31. t plh , t phl , t r and t f test circuit and waveforms. figure 32. cmr test circuit with split resistors network and waveforms. application information product overview description the acpl-h342/k342 is an optically isolated power output stage capable of driving igbts of up to 150 a and 1200 v. it has very high cmr rating which allows the micro - controller and the igbt to operate at very large common mode noise found in industrial motor drives and other power switching applications. and to achieve better system reliability in such noisy environment, this power control device incorporates new features like active miller clamp, rail-to-rail output voltage, anti-cross conduction and led input current hysteresis. active miller clamp function eliminates the need of negative gate drive in most application and allows the use of simple bootstrap supply for high side driver. rail-to- rail output voltage ensures that the igbts gate voltage is driven to the optimum intended level with no power loss across igbt. anti-cross conduction prevents current shoot through between the high and low side of half bridge igbt confguration. this will help to simplify the controller design in terms of having to account for the delay needed at the led input. and lastly, the led input current hyster - esis prevents output oscillation if insufcient led driving current is applied. this will eliminates the need of addi - tional schmitt trigger circuit at the input led. this feature rich igbt gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of external circuitry or control. recommended application circuit the recommended application circuit shown in figure 33 illustrates a typical gate drive implementation using the acpl-h342. the following describes about driving igbt. however, it is also applicable to mosfet. designers will need to adjust the v cc supply voltage, depending on the mosfet or igbt gate threshold requirements (recom - mended v cc = 18v for igbt and 12v for mosfet). the supply bypass capacitors (1 f) provide the large transient currents necessary during a switching transition. because of the transient nature of the charging currents, a low current (2.5ma) power supply will be enough to power the device. the split resistors across the led will provide a high cmr response by providing a balanced re - sistance network across the led. the gate resistor r g serves to limit gate charge current and controls the igbt collector voltage rise and fall times. in pc board design, care should be taken to avoid routing the igbt collector or emitter traces close to the acpl-h342 input as this can result in unwanted coupling of transient signals into acpl-h342 and degrade performance. i f = 7 to 16ma, 20khz, 50% duty cycle + _ 1f v o 1 2 3 4 8 7 6 5 10? 25nf + _ v cc = 15 to 30v v c l a m p v c l a m p i f v out t phl t plh t f t r 10% 50% 90% 5 v + _ 1f v o 1 2 3 4 8 7 6 5 + _ v cm = 1500v 170 ohm 170 ohm + _ + _ + _ + _ v cc = 30v v c l a m p v c l a m p v cm ? t 0 v v o switch at b: i f = 0 ma v o switch at a: i f = 10 ma v ol v oh ? t v cm v t =
15 figure 33. recommended application circuit with split resistors led drive and active miller clamp. + _ 1 2 3 4 8 7 6 5 v cc v out v clamp v ee cathode nc anode + _ r g q1 q2 + v ce - r + hvdc -hvdc 3-phase ac + v ce - 1f r nc v cc =18v + _ + _ + active miller clamp a miller clamp allows the control of the miller current during a high dv/dt situation. and it can also eliminate the use of a negative supply voltage by quickly discharg - ing the large gate capacitance of igbt to low level without afecting the igbt turn-of characteristics. during turn-of, the gate voltage is monitored and the clamp output is activated when gate voltage goes below 2.3v (relative to v ee ). the clamp voltage is v ol +2.5v typ for a miller current up to 2.5 a. the clamp is disabled when the led input is triggered again. an5314 application note describes how the clamp reduces the parasitic turn-on efect due to the miller capacitor and at the same time eliminates the need of a negative power supply. the miller pin should be connected to v ee when not in use. rail-to-rail output figure 34 shows a typical gate drivers high current output stage with 3 bipolar transistors in darlington con - fguration. during the output high transition, the output voltage rises rapidly to within 3 diode drops of v cc . to ensure the v out is at v cc in order to achieve igbt rated v ce(on) voltage. the level of v cc will be need to be raised to beyond v cc +3(v be ) to account for the diode drops. and to limit the output voltage to v cc , a pull-down resistor, r pull-down between the output and v ee is recommended to sink a static current while the output is high. acpl-h342 uses a power nmos follower stage to deliver the initial large current and a smaller pmos to pull it to v cc to achieve rail-to-rail output voltage as shown in figure 35. this ensures that the igbts gate voltage is driven to the optimum intended level with no power loss across igbt even when an unstable power supply is used. figure 34. typical gate driver with output stage in darlington confguration figure 35. acpl-h342 with nmos and pmos output stage for rail-to-rail output voltage 1 2 3 4 8 7 6 5 v cc v out v ee cathode nc anode nc r g r pull-down v cc v out v clamp v ee 1 2 3 4 8 7 6 5 cathode nc anode nc v c l a m p v c l a m p
16 selecting the gate resistor (rg) step 1: calculate rg minimum from the iol peak specifcation. the igbt and rg in figure 33 can be analyzed as a simple rc circuit with a voltage supplied by acpl-h342/k342. rg v cc v ee v ol i olpeak = = 6.28? 7? 18v 0v 2.3v 2.5a the v ol value of 2.3v in the previous equation is the v ol at the peak current of 2.5a (see figure 7). step 1: check the acpl-h342/k342 power dissipation and increase rg if necessary. the acpl-h342/k342 total power dis - sipation (p t ) is equal to the sum of the emitter power (p e ) and the output power (p o ). p t = p e + p o p e = i f ? v f ? duty cycle p o = p o(bias) + p o(switching) = i cc ? (v cc -v ee ) + e sw (rg;qg) ? f using i f (worst case) = 16ma, rg = 7 : , max duty cycle = 80%, qg = 500nc, f = 25khz and t a max = 85c: p e = 16ma ? 1.95v ? 0.8 = 25mw p o = 2.5ma ? 18v + 4j ? 25 khz = 45mw + 100mw = 145mw < 500mw (p o(max) @ 85c) the value of 2.5ma for i cc in the previous equation is the maximum i cc over the entire operating temperature range. since p o is less than p o(max) , rg = 7 : is alright for the power dissipation. 0 1 2 3 4 5 6 7 8 0 10 20 30 40 50 rg - gate resistance - ? esw - energy per switching cycle - j qg = 100nc qg = 500nc qg = 1000nc figure 36. energy dissipated in the acpl-h342/k342 for each igbt switching cycle.
17 anti-cross conduction to prevent current shoot through and determining dead time the acpl-h342 includes a propagation delay diference (pdd = t phl C t plh ) specifcation to help prevent both the high(q1) and low(q2) side power transistors from turning on at the same time. this anti-cross conduction feature prevents large currents from fowing through the power transistors by ensuring t phlmax is faster than t plhmin . in another words, the anti-cross feature will ensure one power transistor is turned of before the other is turned on. a gate driver without anti-cross feature will for example has a pdd min of -350ns and a pdd max of 350ns. a positive pdd max of 350ns would mean one transistor will be turn on before the other is of since t phlmax is longer than t plhmin . this is shown in figure 37. to prevent this and the shoot through current, the turn on of led2 should be delayed (relative to the turn of of led1) so that under worst-case conditions, q1 has just turned of when q2 turns on. the amount of delay to achieve this condition is equal to pdd max as shown in figure 38. figure 38. adding delay to prevent shoot through figure 37. current shoot through without anti-cross feature i led1 i led2 v out1 v out2 q1 on q2 off q1 off q2 on t phlmax t plhmin shoot through i led1 i led2 v out1 v out2 q1 on q2 off q1 off q2 on t phlmax t plhmin pdd max = t phlmax - t plhmin = 350 ns r g q1 q2 r + hvdc -hvdc ac r g r high side pwm low side pwm led1 led2 v out1 v out2
18 the acpl-h342 with the anti-cross feature has a pdd min of -10ns and a pdd max of -200ns. since the pdd is always a negative value, the t phlmax is always faster than t plhmin . thus this simplifed the design without having to add any amount of delay for the input leds as shown in figure 39. symbol min. typ. max. units t plh 0.100 0.260 0.350 s t phl 0.050 0.145 0.250 s pdd (t phl - t plh ) -0.010 -0.100 -0.200 s figure 40. determining maximum dead time dead time is the time period during which both the high(q1) and low(q2) side transistor are of. during this time, no work is done and this reduces the efciency of the inverter or motor drive. the minimum and maximum dead time is shown in figure 39 and 40 and is equivalent to the pdd min and pdd max . due to the smaller pdd and skewed propagation delay confguration, acpl-h342 shows a smaller maximum dead time as compared to its predecessor, hcpl-3120 as shown in fgure 41 and hence an improve in efciency. note that the propagation delays used to calculate pdd and dead time are taken at equal temperature and test conditions since the optocou - plers under consideration are typically mounted in close proximity to each other and are switching identical igbts. figure 39. anti-cross to prevent shoot through figure 41. hcpl-3120 maximum dead time q1 off q2 on i led1 i led2 v out1 v out2 q1 on q2 off t phlmax t plhmin pdd min = -10 ns = minimum dead time t plhmax i led1 i led2 v out1 v out2 q1 off q2 on t plhmin maximum dead time = (t phlmax t phlmin ) + (t plhmax t plhmin ) = (t phlmax t plhmin ) + (t phlmin t plhmax ) = pdd max pdd min = 350 (-350) = 700 ns t plhmax q1 on q2 off t phlmax t phlmin i led1 i led2 v out1 v out2 q1 on q2 off q1 off t phlmin t plhmin t plhmax q2 on pdd max = -200 ns = minimum dead time
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-2526en - march 13, 2013 led input current hysteresis the detector has optical receiver input stage with built in schmitt trigger to provide logic compatible waveforms, eliminating the need for additional wave shaping. the hysteresis (figure 12) provides diferential mode noise immunity and minimizes the potential for output signal chatter. under voltage lockout the acpl-h342 under voltage lockout (uvlo) feature is designed to prevent the application of insufcient gate voltage to the igbt by forcing the acpl-h342 output low during power-up. igbts typically require gate voltages of 15 v to achieve their rated v ce(on) voltage. at gate voltages below 13 v typically, the v ce(on) voltage increases dra - matically, especially at higher currents. at very low gate voltages (below 10 v), the igbt may operate in the linear region and quickly overheat. the uvlo function causes the output to be clamped whenever insufcient operating supply (v cc ) is applied. once v cc exceeds v uvlo+ (the pos - itive-going uvlo threshold), the uvlo clamp is released to allow the device output to turn on in response to input signals. thermal model for acpl-h342/k342 stretched so8 package optocoupler defnitions: r 11 : junction to ambient thermal resistance of led due to heating of led r 12 : junction to ambient thermal resistance of led due to heating of detector (output ic) r 21 : junction to ambient thermal resistance of detector (output ic) due to heating of led. r 22 : junction to ambient thermal resistance of detector (output ic) due to heating of detector (output ic). p 1 : power dissipation of led (w). p 2 : power dissipation of detector / output ic (w). t 1 : junction temperature of led (c). t 2 : junction temperature of detector (c). t a : ambient temperature. ambient temperature: junction to ambient thermal re - sistances were measured approximately 1.25cm above optocoupler at ~23c in still air thermal resistance c/w r 11 145 r 12 , r 21 25, 38 r 22 46 this thermal model assumes that an 8-pin single-channel plastic package optocoupler is soldered into a 7.62 cm x 7.62 cm printed circuit board (pcb) per jedec standards. the temperature at the led and detector junctions of the optocoupler can be calculated using the equations below. t 1 = (r 11 * p 1 + r 12 * p 2 ) + t a (1) t 2 = (r 21 * p 1 + r 22 * p 2 ) + t a (2) using the given thermal resistances and thermal model formula in this datasheet, we can calculate the junction temperature for both led and the output detector. both junction temperature should be within the absolute maxi mum rating. for example, given p 1 = 45 mw, p 2 =210 mw, ta = 85c: led junction temperature, t 1 = (r 11 * p 1 + r 12 * p 2 ) + t a = (145 * 0.045 + 25 * 0.210) + 85 = 97c output ic junction temperature, t 2 = (r 21 x p 1 + r 22 x p 2 ) + t a = (38 *0.045 + 46 * 0.210) + 85 = 96 c t 1 and t 2 should be limited to 125c based on the board layout and part placement. related application noted an5336 C gate drive optocoupler basic design for igbt/ mosfet an1043 C common-mode noise: sources and solutions an02-0310en C plastics optocouplers product esd and moisture sensitivity

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